DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 587
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 587 of 1154
- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–53. PCIe Rateswitch Controller and Clock Switch Circuitry
February 2011 Altera Corporation
Channel
Bonding
Option
×1
×4
×8
Individual channel PCS block
CMU0_Channel
CMU0_Channel of the master
transceiver block
Location of PCIe Rateswitch
Controller Module
PCIe transmitter high-speed serial and low-speed parallel clock switch occurs:
■
■
■
In PCIe ×1, ×4, and ×8 modes, the recovered clock switch happens in the receiver CDR
of each transceiver channel.
Table 1–53
switch circuitry in PCIe ×1, ×4, and ×8 modes.
In PCIe ×1 mode, the CMU_PLL clock switch occurs in the local clock divider in each
transceiver channel.
In PCIe ×4 mode, the CMU_PLL clock switch occurs in the CMU0 clock divider in the
CMU0_Channel within the transceiver block.
In PCIe ×8 mode, the CMU_PLL clock switch occurs in the CMU0 clock divider in the
CMU0_Channel within the master transceiver block.
lists the locations of the PCIe rateswitch controller and the PCIe clock
Local clock divider in transmitter PMA
of each channel
CMU0 clock divider in CMU0_Channel
CMU0 clock divider in CMU0_Channel
of the master transceiver block
Transmitter High-Speed Serial and
Low-Speed Parallel Clock Switch
Circuitry
Location of PCIe Clock Switch Circuitry
Stratix IV Device Handbook Volume 2: Transceivers
Recovered Clock Switch Circuitry
CDR block in receiver PMA of each
channel
CDR block in receiver PMA of each
channel
CDR block in receiver PMA of each
channel
1–143
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