DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 683

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric PLLs-Transceiver PLLs Cascading
Figure 2–6. FPGA Fabric PLLs-Transceiver PLLs Cascading Options Allowed for 1152-Pin Package Devices
February 2011 Altera Corporation
FPGA Fabric PLLs-Transceiver PLLs Cascading in the 780-Pin Package
FPGA Fabric PLLs-Transceiver PLLs Cascading in the 1152-Pin Package
Transceiver Block GXBL1
Transceiver Block GXBL0
Channel 3
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 2
ATX PLL L0 (6G)
CMU1
CMU0
CMU1
CMU0
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
PLL
PLL
PLL
PLL
Stratix IV GX devices in 780-pin packages do not support FPGA fabric
PLLs-transceiver PLLs cascading.
Figure 2–6
in the EP4SGX110FF35 device (red), the EP4SGX230FF35, EP4SGX290FF35 and
EP4SGX360FF35 devices (blue), and the EP4SGX530HH35 device (black).
Cascade
Network
PLL
shows the FPGA fabric PLLs-Transceiver PLLs cascading options allowed
PLL_L2
EP4SGX110FF35
EP4SGX530HH35
EP4SGX230FF35
EP4SGX290FF35
EP4SGX360FF35
PLL_R2
Stratix IV Device Handbook Volume 2: Transceivers
Cascade
Network
PLL
Transceiver Block GXBR1
Transceiver Block GXBR0
ATX PLL R0 (6G)
CMU1
CMU0
CDR
CMU0
CDR
CMU1
CDR
CDR
CDR
CDR
CDR
CDR
PLL
PLL
PLL
PLL
Channel 0
Channel 3
Channel 0
Channel 3
Channel 2
Channel 1
Channel 2
Channel 1
2–11