DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 348
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 348 of 1154
- Download datasheet (32Mb)
10–14
Figure 10–5. FPP Configuration Timing Waveform with Decompression or Design Security Feature Enabled
Notes to
(1) Use this timing waveform when you have enabled the decompression and/or design security features.
(2) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
(3) After power-up, the Stratix IV device holds nSTATUS low for the time of the POR delay.
(4) After power-up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) DATA[7..0] are available as user I/O pins after configuration except for some exceptions on Stratix IV GT devices. The state of these pins
(7) If needed, you can pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[7..0] pins prior to
Table 10–5. FPP Timing Parameters for Stratix IV Devices with the Decompression and/or Design Security Features
Enabled
Stratix IV Device Handbook Volume 1
t
t
t
t
t
t
Symbol
CF2CD
CF2ST0
CFG
STATUS
CF2ST1
CF2CK
CONF_DONE
When nCONFIG is pulled low, a reconfiguration cycle begins.
depends on the dual-purpose pin settings.
sending the first DCLK rising edge.
nSTATUS (3)
INIT_DONE
DATA[7..0]
nCONFIG
Figure
User I/O
(Note
DCLK
nCONFIG low to CONF_DONE
low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS
high
nCONFIG high to first rising
edge on DCLK
(4)
10–5:
1),
t
t
(2)
CFG
CF2CD
Parameter
t
CF2ST1
t
Figure 10–5
MAX II device as an external host. This waveform shows the timing when you have
enabled the decompression and/or design security features.
Table 10–5
when you enable the decompression and/or the design security features.
CF2ST0
(Part 1 of 2)
t
CF2CK
t
ST2CK
t
STATUS
t
High-Z
DSU
1
2
Byte 0
t
lists the timing parameters for Stratix IV devices for an FPP configuration
DH
shows the timing waveform for an FPP configuration when using a
3
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
4
Stratix IV
1
(7)
t
CH
2
t
Byte 1
CLK
t
t
CL
DH
3
Stratix IV
Minimum
4
500
—
—
10
—
(8)
2
(7)
Stratix IV
Byte 2
(9)
1
Stratix IV
Byte (n-1)
(7)
3
4
Maximum
Stratix IV
Fast Passive Parallel Configuration
Byte n
500
500
800
800
April 2011 Altera Corporation
—
—
(8)
t
CD2UM
(3)
(4)
Stratix IV
(5)
(6)
(9)
User Mode
User Mode
(Note
1),
Units
ns
ns
μ s
μ s
μ s
μ s
(2)
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