DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 966

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–8
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 5 of 10)
Stratix IV Device Handbook Volume 3
What is the deserializer block
width?
ALTGX Setting
Basic
Basic (PMA Direct)
Deterministic Latency
This option sets the transceiver data path width.
■
■
GIGE
PCIe
SDI
Serial RapidIO
XAUI
These modes only operate in single-width mode.
Double-width mode is not allowed.
(OIF) CEI PHY Interface
The (OIF) CEI PHY Interface mode only operates in
double-width mode. Single-width mode is not allowed.
SONET/SDH
This option allows you to set the transceiver data path
width.
■
■
Single-width—This mode operates from 600 Mbps to
3.75 Gbps.
Double-width—This mode operates from 1 Gbps to
8.5 Gbps.
Single-width—Selected automatically in OC-12 and
OC-48 configurations. The transceiver data path width
is 8 bits.
Double-width—Selected automatically in OC-96
configurations. The transceiver data path width is
16 bits.
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
“Basic Single-Width Mode
Configurations” and “Basic
Double-Width Mode
Configurations” sections in the
Transceiver Architecture in
Stratix IV Devices
February 2011 Altera Corporation
Reference
—
—
—
Parameter Settings
chapter.