DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 164

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–48
Figure 5–41. Scan-Chain Order of PLL Components for Top and Bottom PLLs
Note to
(1) Left and right PLLs have the same scan-chain order. The post-scale counters end at C6.
Figure 5–42. Scan-Chain Bit-Order Sequence for Post-Scale Counters in Stratix IV PLLs
Stratix IV Device Handbook Volume 1
Figure
DATAOUT
5–41:
DATAIN
HB
LB
0
0
Table 5–11. Top and Bottom PLL Reprogramming Bits (Part 2 of 2)
Table 5–11
which have 10 post-scale counters. The order of bits is the same for the left and right
PLLs, but the reconfiguration bits start with the C6 post-scale counter.
Figure 5–41
PLLs.
Figure 5–42
Stratix IV PLLs.
Loop Filter Capacitor
Loop Filter Resistor
Unused CP/LF
Total number of bits
Notes to
(1) Includes two control bits, rbypass, for bypassing the counter, and rselodd, to select the output clock duty
(2) The LSB for the C9 low-count value is the first bit shifted into the scan chain for the top and bottom PLLs.
(3) The LSB for the C6 low-count value is the first bit shifted into the scan chain for the left and right PLLs.
(4) The MSB for the loop filter is the last bit shifted into the scan chain.
cycle.
HB
C6
C7
LB
1
1
Table
MSB
lists the scan chain order of PLL components for the top and bottom PLLs,
Block Name
shows the scan-chain order of PLL components for the top and bottom
shows the scan-chain bit-order sequence for post-scale counters in all
5–11:
HB
LB
LF
2
2
C8
C5
K
(4)
HB
LB
3
3
CP
C9
HB
C4
LB
4
4
LSB
HB
Counter
LB
5
5
DATAOUT
—
0
0
0
C3
N
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Number of Bits
HB
LB
6
6
(Note 1)
Other
HB
LB
C2
7
7
M
—
2
5
7
(1)
February 2011 Altera Corporation
rselodd
rbypass
C1
C0
PLLs in Stratix IV Devices
Total
234
2
5
7
DATAIN