DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 743

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
Table 2–17. Receiver Phase Compensation FIFO Write Clocks
February 2011 Altera Corporation
Non-Bonded Channel
Configuration with rate
matcher
Non-Bonded Channel
Configuration without rate
matcher
×4-Bonded Channel
Configuration
×8-Bonded Channel
Configuration
Configuration
1
1
Table 2–17
software selects in various configurations.
To ensure that you understand the 0 PPM clock driver rule, the Quartus II software
expects the following user assignment whenever you use the rx_coreclk port to drive
the receiver phase compensation FIFO read clock:
■
Failing to make this assignment correctly when using the rx_coreclk port results in a
Quartus II compilation error.
The GXB 0 PPM core clock setting user assignment allows the following clock
drivers to drive the rx_coreclk ports:
■
■
■
■
■
■
The Quartus II software does not allow gated clocks or clocks generated in FPGA
logic to drive the tx_coreclk ports.
Because the 0 PPM clock group assignment allows the FPGA CLK input pins and
transceiver refclk pins as the clock driver, the Quartus II compiler cannot determine
if there is a 0 PPM difference between the FIFO write clock and read clock for each
channel.
GXB 0 PPM Core Clock Setting
tx_clkout in non-bonded channel configurations with rate matcher
tx_clkout and rx_clkout in non-bonded configurations without rate matcher
coreclkout in bonded channel configurations
FPGA CLK input pins
Transceiver refclk pins
Clock output from left and right and top and bottom PLLs (PLL_L, PLL_R, and
PLL_T, PLL_B)
Low-speed parallel clock from the local
clock divider in the associated channel
(tx_clkout)
Parallel recovered clock from the receiver
PMA in the associated channel
(rx_clkout)
Low-speed parallel clock from the CMU0
clock divider of the associated transceiver
block (coreclkout)
Low-speed parallel clock from the CMU0
clock divider of the master transceiver
block (coreclkout from the master
transceiver block)
lists the receiver phase compensation FIFO write clocks that the Quartus II
Without Byte Serializer
Receiver Phase Compensation FIFO Write Clock
Divide-by-two version of the low-speed
parallel clock from the local clock divider in
the associated channel (tx_clkout)
Divide-by-two version of the parallel
recovered clock from the receiver PMA in the
associated channel (rx_clkout)
Divide-by-two version of the low-speed
parallel clock from the CMU0 clock divider of
the associated transceiver block
(coreclkout)
Divide-by-two version of the low-speed
parallel clock from the CMU0 clock divider of
the master transceiver block (coreclkout
from the master transceiver block)
Stratix IV Device Handbook Volume 2: Transceivers
With Byte Serializer
2–71