DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 695

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Figure 2–14. Transmitter Channel Clocking Configurations
February 2011 Altera Corporation
Non-Bonded
Non-bonded and bonded configurations use the following:
■
■
■
ATX PLLs always use ×N lines to distribute the high-speed serial and low-speed
parallel transceiver clocks. Use the ×N_Top line if the CMU0 PLL or ATX PLL that
generates the transceiver clocks is located at the top of the transmitter channel. Use
the ×N_Bottom line if the CMU0 PLL or ATX PLL is located at the bottom of the
transmitter channel. Because there is only one ×N_Top and ×N_Bottom line on each side
of the device, using an ATX PLL limits the use of the ×N clock lines to distribute the
transceiver clocks to other transmitter channels in the design.
Transmitter Channel Clocking Configurations
Figure 2–14
Transmitter channels configured in modes other than Basic (PMA Direct) mode use
both the transmitter channel PCS and PMA blocks. As a result, Stratix IV devices
allow placing these transmitter channels only in the four regular channels of a
transceiver block. Stratix IV devices do not allow configuring the CMU channels in
any mode other than Basic (PMA Direct) mode because of the absence of PCS blocks
in the CMU channels.
×1 non-bonded configurations use the ×1 clock lines to distribute only the
high-speed serial transceiver clock synthesized by the CMU0 PLL or CMU1 PLL to the
clock transmitter channels located in the same transceiver block. The low-speed
parallel transceiver clock is generated in the transceiver channels using the local
clock dividers.
×4 bonded configurations use the ×4_GXB clock lines to distribute both the
high-speed serial and low-speed parallel transceiver clocks generated by the
CMU0_Channel to clock the bonded transmitter channels located in the same
transceiver block.
×8 and ×N bonded configurations use the ×N_Top or ×N_Bottom clock lines to
distribute both the high-speed serial and low-speed parallel transceiver clocks
generated by the CMU0 channel block to all bonded transmitter channels located
across transceiver blocks.
Bonded
x4
shows various transmitter channel clocking configurations.
Bonded
Bonded
Transmitter Channel Clocking
x8
Configurations
Basic (PMA Direct)
Non-Bonded
Stratix IV Device Handbook Volume 2: Transceivers
Basic (PMA Direct) xN
Bonded
2–23