DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 223

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Memory Interfaces Pin Support
February 2011 Altera Corporation
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1
A typical memory interface requires data (D, Q, or DQ), data strobe (DQS/CQ and
DQSn/CQn), address, command, and clock pins. Some memory interfaces use data
mask (DM, BWSn, or NWSn) pins to enable write masking and QVLD pins to indicate
that the read data is ready to be captured. This section describes how Stratix IV
devices support all these different pins.
If you have more than one clock pair, you must place them in the same DQ group. For
example, if you have two clock pairs, you must place both of them in the same ×4
DQS group.
For more information about pin connections, refer to the
Device Family Pin Connection
For more information about pin planning and pin connections between a Stratix IV
device and an external memory device, refer to the
Handbook.
DDR3, DDR2, DDR SDRAM, and RLDRAM II devices use the CK and CK# signals to
capture the address and command signals. Generate these signals to mimic the
write-data strobe using Stratix IV DDR I/O registers (DDIOs) to ensure that the
timing relationships between the CK/CK# and DQS signals (t
DDR3, DDR2, and DDR SDRAM devices or t
QDR II+ and QDR II SRAM devices use the same clock (K/K#) to capture write data,
address, and command signals.
Memory clock pins in Stratix IV devices are generated using a DDIO register going to
differential output pins (refer to
DIFFIO_TX, or DIFFIO_RX prefixes.
For more information about which pins to use for memory clock pins, refer to the
External Memory Interface
Handbook.
Guidelines.
Figure
7–2), marked in the pin table with DIFFOUT,
CKDK
in RLDRAM II devices) are met.
External Memory Interface
Stratix IV GX and Stratix IV E
Stratix IV Device Handbook Volume 1
DQSS
, t
DSS
, and t
DSH
in
7–3