DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 61
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 61 of 1154
- Download datasheet (32Mb)
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview
February 2011 Altera Corporation
Address Clock Enable Support
All Stratix IV memory blocks support address clock enable, which holds the previous
address value for as long as the signal is enabled (addressstall = 1). When the
memory blocks are configured in dual-port mode, each port has its own independent
address clock enable. The default value for the address clock enable signals is low
(disabled).
Figure 3–2
referred to by the port name addressstall.
Figure 3–2. Address Clock Enable
Figure 3–3
Figure 3–3. Address Clock Enable During Read Cycle Waveform
latched address
(inside memory)
addressstall
q (asynch)
rdaddress
q (synch)
shows an address clock enable block diagram. The address clock enable is
shows the address clock enable waveform during the read cycle.
inclock
rden
doutn-1
doutn
addressstall
an
address[0]
address[N]
a0
clock
doutn
a0
dout0
a1
1
0
dout0
1
0
a2
address[0]
address[N]
register
register
a1
dout1
a3
dout1
address[0]
address[N]
Stratix IV Device Handbook Volume 1
a4
a4
dout4
a5
dout4
a5
dout5
a6
3–5
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