DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 209
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 209 of 1154
- Download datasheet (32Mb)
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
February 2011 Altera Corporation
OCT Calibration
Figure 6–25
(where N is a calibration block number), you must assert ENAOCT one cycle before
asserting ENASER[N]. Also, nCLRUSR must be set to low for one OCTUSRCLK cycle before
the ENASER[N] signal is asserted. Assert the ENASER[N] signals for 1000 OCTUSRCLK
cycles to perform OCTRS and OCTRT calibration. You can de-assert ENAOCT one clock
cycle after the last ENASER is de-asserted.
Serial Data Transfer
After you complete calibration, you must serially shift out the 28-bit OCT calibration
codes (14-bit OCT R
corresponding I/O buffers. Only one OCT calibration block can send out the codes at
any time by asserting only one ENASER[N] signal at a time. After you de-assert ENAOCT,
wait at least one OCTUSRCLK cycle to enable any ENASER[N] signal to begin serial
transfer. To shift the 28-bit code from the OCT calibration block[N], you must assert
ENASER[N] for exactly 28 OCTUSRCLK cycles. Between two consecutive asserted ENASER
signals, there must be at least one OCTUSRCLK cycle gap.
Figure 6–25. OCT User Mode Signal—Timing Waveform for One OCT Block
Note to
(1) t
After calibrated codes are shifted in serially to each I/O bank, the calibrated codes
must be converted from serial to parallel format before being used in the I/O buffers.
Figure 6–25
calibration codes in each I/O bank. All I/O banks that received the codes from the
same OCT calibration block can have S2PENA asserted at the same time, or at a
different time, even while another OCT calibration block is calibrating and serially
shifting codes. The S2PENA signal is asserted one OCTUSRCLK cycle after ENASER is
de-asserted for at least 25 ns. You cannot use I/Os for transmitting or receiving data
when their S2PENA is asserted for parallel codes transfer.
s2p
Figure
≥ 25 ns.
OCTUSRCLK
S2PENA_1A
nCLRUSR
ENASER0
ENAOCT
6–25:
shows user mode signal-timing waveforms. To calibrate OCT block[N]
shows the S2PENA signals that can be asserted at any time to update the
S
and 14-bit OCT R
1000 OCTUSRCLK Cycles
Calibration Phase
T
) from each OCT calibration block to the
OCTUSRCLK
(Figure
Cycles
28
Stratix IV Device Handbook Volume 1
6–25).
t s2p
(1)
6–37
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