DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 289

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Transmitter
Table 8–7. Port List of the LVDS Interface (ALTLVDS)
Differential Transmitter
February 2011 Altera Corporation
dpa_pll_cal_busy
rx_reset
rx_fifo_reset
rx_cda_reset
Notes to
(1) Unless stated, signals are valid in all three modes (non-DPA, DPA, and soft-CDR) for a single channel.
(2) All reset and control signals are active high.
(3) For more information, refer to
Reset Signals
Table
Port Name
8–7:
f
1
For more information about the LVDS transmitter and receiver settings using
ALTLVDS, refer to the
The Stratix IV transmitter has a dedicated circuitry to provide support for LVDS
signaling. The dedicated circuitry consists of a differential buffer, a serializer, and left
and right PLLs that can be shared between the transmitter and receiver. The
differential buffer can drive out LVDS, mini-LVDS, and RSDS signaling levels. The
serializer takes up to 10 bits wide parallel data from the FPGA fabric, clocks it into the
load registers, and serializes it using shift registers clocked by the left and right PLL
before sending the data to the differential buffer. The MSB of the parallel data is
transmitted first.
When using emulated LVDS I/O standards at the differential transmitter, the
SERDES circuitry must be implemented in logic cells but not hard SERDES.
“LVDS Interface with the Use External PLL Option Enabled” on page
Output
Input
Input
Input
Output
Input /
Busy signal that is asserted high when the PLL calibration occurs.
Asynchronous reset to the DPA circuitry and FIFO. The minimum pulse
width requirement for this reset is one parallel clock cycle. This signal
resets DPA and FIFO blocks.
Asynchronous reset to the FIFO between the DPA and the data realignment
circuits. The synchronizer block must be reset after a DPA loses lock
condition and the data checker shows corrupted received data. The
minimum pulse width requirement for this reset is one parallel clock cycle.
This signal resets the FIFO block.
Asynchronous reset to the data realignment circuitry. The minimum pulse
width requirement for this reset is one parallel clock cycle. This signal
resets the data realignment block.
ALTLVDS Megafunction User
(Note
1),
(2)
(Part 3 of 3)
Description
Guide.
8–26.
Stratix IV Device Handbook Volume 1
8–11