DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 113

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Figure 4–21. Rounding and Saturation Locations
February 2011 Altera Corporation
16 User defined SAT Positions (bit 43-28)
43
43
1
1
1
42
42
Two saturation modes are supported in Stratix IV:
■
■
You must select one of the two options at compile time.
In 2’s-complement format, the maximum negative number that can be represented is
–2
the maximum negative number to –2
■
■
Table 4–8
36-bits.
Table 4–8. Examples of Saturation
Stratix IV devices have up to 16 configurable bit positions out of the 44-bit bus
([43:0]) for the rounding and saturate logic unit, providing higher flexibility. These
16-bit positions are located at bits [21:6] for rounding and [43:28] for saturation, as
shown in
You must select the 16 configurable bit positions at compile time.
For symmetric saturation, the RND bit position is also used to determine where the
LSP for the saturated data is located.
(n –1)
Asymmetric saturation mode
Symmetric saturation mode
Asymmetric 32-bit saturation: Max = 0x7FFFFFFF, Min = 0x80000000
Symmetric 32-bit saturation: Max = 0x7FFFFFFF, Min = 0x80000001
44- to 36-Bits Saturation
, while the maximum positive number is 2
5926AC01342h
ADA38D2210h
lists how saturation works. In this example, a 44-bit input is saturated to
Figure
29
4–21.
28
16 User defined RND Positions (bit 21-6)
21
20
Symmetric SAT Result
800000001h
(n–1)
7FFFFFFFFh
+ 1. For example, for 32 bits:
(n–1)
– 1. Symmetrical saturation limits
7
6
Stratix IV Device Handbook Volume 1
Asymmetric SAT Result
800000000h
7FFFFFFFFh
1
0
0
4–33