DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 129

DK-DEV-4SGX230N

Manufacturer Part Number

DK-DEV-4SGX230N

Description

KIT DEVELOPMENT STRATIX IV

Manufacturer

Altera

Series

Stratix® IVr

Type

FPGAr

Datasheets

1.EP4SGX110DF29C3N.pdf (80 pages)

2.EP4SGX110DF29C3N.pdf (1154 pages)

3.DK-DEV-4SGX230N.pdf (2 pages)

4.DK-DEV-4SGX530N.pdf (57 pages)

Specifications of DK-DEV-4SGX230N

Contents

Development Board, Universal Power Supply, Cables and Software

Silicon Manufacturer

Altera

Core Architecture

FPGA

Core Sub-architecture

Stratix

Silicon Core Number

EP4S

Silicon Family Name

Stratix IV GX

Rohs Compliant

Yes

For Use With/related Products

EP4SGX230K

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

544-2594

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

DK-DEV-4SGX230N

Manufacturer:

Altera

Quantity:

135

Company:

BOSTOCK HK LIMITED

Part Number:

DK-DEV-4SGX230N

Manufacturer:

ALTERA

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Chapter 5: Clock Networks and PLLs in Stratix IV Devices

Clock Networks in Stratix IV Devices

February 2011 Altera Corporation

Clock Output Connections

Dedicated clock pins can drive PLLs over dedicated routing; they do not require the

global or regional network. Compensated inputs, which are a subset of dedicated

clock pins, drive PLLs that can only compensate the input delay when a dedicated

clock pin is in the same I/O bank as the PLL used.

PLLs in Stratix IV devices can drive up to 20 RCLK networks and four GCLK

networks. For Stratix IV PLL connectivity to GCLK networks, refer to

Quartus II software automatically assigns PLL clock outputs to RCLK and GCLK

networks.

Table 5–5

Table 5–5. Stratix IV PLL Connectivity to the GCLK Networks

Table 5–6

Table 5–6. Stratix IV RCLK Outputs From the PLL Clock Outputs

GCLK0

GCLK1

GCLK2

GCLK3

GCLK4

GCLK5

GCLK6

GCLK7

GCLK8

GCLK9

GCLK10

GCLK11

GCLK12

GCLK13

GCLK14

GCLK15

Note to

(1) Only PLL counter outputs C0 - C3 can drive the GCLK networks.

RCLK[0..11]

RCLK[12..31]

RCLK[32..43]

RCLK[44..63]

Clock Resource

Clock Network

Table

lists how the PLL clock outputs connect to the GCLK networks.

lists how the PLL clock outputs connect to the RCLK networks.

5–5:

—

PLL Number

—

(Note 1)

Stratix IV Device Handbook Volume 1

—

(Part 1 of 2)

—

Table

—

5–5. The

—

5–13

—

DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 129

DK-DEV-4SGX230N

Specifications of DK-DEV-4SGX230N

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