DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 903

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–28. Incorrect Input Reference Clock Connections When Reusing a .mif
Note to
(1) The red lines represent the alternate source of REFCLK.
February 2011 Altera Corporation
Figure
5–28:
f
156.25 MHz
125 MHz
For more information about input reference clocking, refer to the “Input Reference
Clocking” section of the
The following section describes the clocking requirements to re-use .mifs.
The .mif contains information about the input clock multiplexer settings and the
functional blocks that you selected during the ALTGX MegaWizard Plug-In Manager
instantiation. You can use a .mif to dynamically reconfigure any of the other
transceiver channels in the device as long as the order of the clock inputs is consistent.
For example, assume that a .mif is generated for a transceiver channel in transceiver
block 0 and the input clock source is connected to the pll_inclk_rx_cruclk[0] port.
When you use the generated .mif for a channel in other transceiver blocks (for
example, transceiver block 1), the same clock source must be connected to the
pll_inclk_rx_cruclk[0] port.
correct order of input reference clocks, respectively.
In
reference clock is not connected to the corresponding pll_inclk_rx_cruclk[] ports in
the two instances.
Figure
5–28, the clocking is incorrect when re-using the .mif because the input
(1)
Transceiver Clocking in Stratix IV Devices
(1)
Figure 5–28
pll_inclk_rx_cruclk[0]
pll_inclk_rx_cruclk[1]
pll_inclk_rx_cruclk[0]
pll_inclk_rx_cruclk[1]
Stratix IV GX Device
and
Figure 5–29
Stratix IV Device Handbook Volume 2: Transceivers
Transceiver Block 0
Transceiver Block 1
show the incorrect and
Instance 1
Instance 2
ALTGX
ALTGX
chapter.
5–57