DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 692

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–20
Transceiver Channel Datapath Clocking
Stratix IV Device Handbook Volume 2: Transceivers
Transmitter Channel Datapath Clocking
f
1
This section describes the transmitter channel and receiver channel datapath clocking
in various configurations. Datapath clocking varies with physical coding sublayer
(PCS) configurations in different functional modes as well as channel bonding
options. This section contains:
■
■
Clocking described in this section is internal to the transceiver and clock routing is
primarily performed by the Quartus II software.
For more information about manually picking and placing CMU and ATX PLLs, refer
to
Devices.
This section describes the transmitter channel PMA and PCS datapath clocking in
non-bonded and bonded channel configurations:
■
■
■
■
AN 578: Manual Placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT
“Transmitter Channel Datapath Clocking” on page 2–20
“Receiver Channel Datapath Clocking” on page 2–39
“Non-Bonded Channel Configurations” on page 2–24
“Bonded Channel Configurations” on page 2–27
“Non-Bonded Basic (PMA Direct) Mode Channel Configurations” on page 2–34
“Bonded Basic (PMA Direct) ×N Mode Channel Configurations” on page 2–36
Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation