DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 621

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–65. Word Aligner Settings
February 2011 Altera Corporation
Serial Bit Transmission Order
MSB-to-LSB
MSB-to-LSB
LSB-to-MSB
You can configure the word aligner to flip the alignment pattern bits programmed in
the MegaWizard Plug-In Manager and compare them with the incoming data for
alignment. This feature offers flexibility to the SONET backplane system for either a
MSB-to-LSB or LSB-to-MSB data transfer.
that you must program in the ALTGX MegaWizard Plug-In Manager based on the
bit-transmission order and the word aligner bit-flip option.
The behavior of the SONET/SDH word aligner control and status signals, along with
an operational timing diagram, are explained in
with 8-Bit PMA-PCS Interface Modes” on page
OC-48 and OC-96 Byte Serializer and Deserializer
The OC-48 and OC-96 transceiver datapath includes the byte serializer and
deserializer to allow the PLD interface to run at a lower speed. The OC-12
configuration does not use the byte serializer and deserializer blocks.
The byte serializer and deserializer blocks are explained in
page 1–21
The OC-48 byte serializer converts 16-bit data words from the FPGA fabric and
translates the 16-bit data words into two 8-bit data bytes at twice the rate. The OC-48
byte deserializer takes in two consecutive 8-bit data bytes and translates them into a
16-bit data word to the FPGA fabric at half the rate.
The OC-96 byte serializer converts 32-bit data words from the FPGA fabric and
translates them into two 16-bit data words at twice the rate. The OC-96 byte
deserializer takes in two consecutive 16-bit data words and translates them into a
32-bit data word to the FPGA fabric at half the rate.
OC-48 Byte Ordering
Because of byte deserialization, the MSByte of a word might appear at the rx_dataout
port along with the LSByte of the next word.
In an OC-48 configuration, the byte ordering block is built into the datapath and can
be leveraged to perform byte ordering. Byte ordering in an OC-48 configuration is
automatic, as explained in
In automatic mode, the byte ordering block is triggered by the rising edge of the
rx_syncstatus signal. As soon as the byte ordering block sees the rising edge of the
rx_syncstatus signal, it compares the LSByte coming out of the byte deserializer with
the A2 byte of the A1A2 alignment pattern. If the LSByte coming out of the byte
deserializer does not match the A2 byte set in the ALTGX MegaWizard Plug-In
Manager, the byte ordering block inserts a PAD character, as seen in
Insertion of this PAD character enables the byte ordering block to restore the correct
byte order.
and
“Byte Deserializer” on page
Word Alignment Bit Flip
“Word-Alignment-Based Byte Ordering” on page
On
Off
Off
Table 1–65
1–92, respectively.
1–60.
“Word Aligner in Single-Width Mode
Stratix IV Device Handbook Volume 2: Transceivers
lists word alignment patterns
1111011000101000 (16'hF628)
0001010001101111 (16'h146F)
0010100011110110 (16'h28F6)
Word Alignment Pattern
“Byte Serializer” on
Figure
1–144.
1–97.
1–177