DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 550

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–106
Figure 1–92. CMU1 Channel (Grayed Area Shows the Inactive Block)
Stratix IV Device Handbook Volume 2: Transceivers
f
f
CMU1 Channel
The CMU1 channel, shown in
high-speed clock to the transmitter channels within the transceiver block. The
CMU1 PLL is similar to the CMU0 PLL (refer to
The CMU1 PLL generates the high-speed clock that is only used in non-bonded
functional modes. The transmitter channels within the transceiver block can receive a
high-speed clock from either of the two CMU PLLs and uses local dividers to provide
clocks to its PCS and PMA blocks.
For more information about using two CMU PLLs to configure transmitter channels,
refer to the
Power Down CMU1 PLL
You can power down the CMU1 PLL by asserting the pll_powerdown signal.
For more information, refer to the
chapter.
Configuring CMU Channels as Transceiver Channels
You can configure the two CMU channels in the transceiver block of Stratix IV GX
and GT devices as full-duplex PMA-only channels to run between 600 Mbps and
6.5 Gbps.
PLL Cascade Clock
Global Clock Line
Dedicated refclk0
Dedicated refclk1
ITB Clock Lines
pll_powerdown
pll_locked
Configuring Multiple Protocols and Data Rates in Stratix IV Devices
6
CMU1 PLL
Reference
Input
Clock
Figure
CMU1 PLL
Reset Control and Power Down in Stratix IV Devices
1–92, contains the CMU1 PLL that provides the
Chapter 1: Transceiver Architecture in Stratix IV Devices
“CMU0 PLL” on page
CMU1 PLL
High-Speed
Clock
CMU1 Channel
CMU1 Clock
Divider
February 2011 Altera Corporation
Transceiver Block Architecture
1–102).
chapter.