DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 68

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

3–12
Figure 3–10. Simple Dual-Port Timing Waveforms
Figure 3–11. Mixed-Port Read-During-Write Timing Waveforms
Stratix IV Device Handbook Volume 1
q (asynch)
q (asynch)
wraddress
wraddress
rdaddress
rdaddress
wrclock
wrclock
rdclock
rdclock
wren
data
wren
data
rden
rden
din-1
doutn-1
din-1
doutn-1
an-1
an-1
Figure 3–10
dual-port mode with unregistered outputs. Registering the RAM outputs simply
delays the q output by one clock cycle.
Figure 3–11
mode with unregistered outputs.
bn
bn
an
an
din
din
shows timing waveforms for read and write operations in mixed-port
shows timing waveforms for read and write operations in simple
doutn
doutn
b0
b0
a0
a0
a1
a1
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
dout0
dout0
a2
b1
a2
b1
a3
a3
din4
din4
b2
b2
a4
a4
February 2011 Altera Corporation
din5
din5
a5
a5
b3
b3
a6
a6
din6
din6
Memory Modes