DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 175

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 6: I/O Features in Stratix IV Devices
I/O Standards Support
Table 6–2. I/O Standards and Voltage Levels for Stratix IV Devices
February 2011 Altera Corporation
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
3.0-V PCI
3.0-V PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
I/O Standard
I/O Standards and Voltage Levels
f
(3)
JESD8-9B
JESD8-9B
JESD8-11
JESD8-12
JESD8-15
JESD8-15
Table 6–1. I/O Standards and Applications for Stratix IV Devices (Part 2 of 2)
For more information about transceiver supported I/O standards, refer to the
Transceiver Architecture in Stratix IV Devices
Stratix IV devices support a wide range of industry I/O standards, including
single-ended, voltage-referenced single-ended, and differential I/O standards.
Table 6–2
V
Standard
JESD8-B
JESD8-B
JESD8-5
JESD8-7
Support
Differential HSTL-15 Class I and II
Differential HSTL-12 Class I and II
LVDS
RSDS
mini-LVDS
LVPECL
Notes to
(1) The 3.3-V LVTTL/LVCMOS standard is supported using V
(2) For more information about the 3.3-V LVTTL/LVCMOS standard supported in Stratix IV devices, refer to
Rev 2.1
Rev 1.0
CCIO
PCI-X
PCI
—
—
Interface” on page
, V
Table
CCPD
lists the supported I/O standards and typical values for input and output
I/O Banks
Column
6–1:
3.0/2.5
3.0/2.5
3.0/2.5
1.8/1.5
1.8/1.5
, V
Input Operation
1.2
3.0
3.0
(2)
(2)
(2)
(2)
(2)
(2)
REF
I/O Standard
6–19.
, and board V
I/O Banks
3.0/2.5
3.0/2.5
3.0/2.5
1.8/1.5
1.8/1.5
Row
1.2
3.0
3.0
(2)
(2)
(2)
(2)
(2)
(2)
V
CCIO
TT
(V)
I/O Banks
Column
.
Output Operation
3.0
3.0
2.5
1.8
1.5
1.2
3.0
3.0
2.5
2.5
1.8
1.8
1.5
1.5
(Note 1)
chapter.
I/O Banks
High-speed communications
Flat panel display
Video graphics and clock distribution
Clock interfaces
Clock interfaces
Flat panel display
CCIO
Row
3.0
3.0
2.5
1.8
1.5
1.2
3.0
3.0
2.5
2.5
1.8
1.8
1.5
—
(Part 1 of 3)
at 3.0 V.
(Pre-Driver
V
Voltage)
CCPD
3.0
3.0
2.5
2.5
2.5
2.5
3.0
3.0
2.5
2.5
2.5
2.5
2.5
2.5
Stratix IV Device Handbook Volume 1
Application
(V)
(Input Ref
Voltage)
V
REF
1.25
1.25
0.90
0.90
0.75
0.75
—
—
—
—
—
—
—
—
(V)
Termination
Voltage)
“3.3-V I/O
(Board
V
1.25
1.25
0.90
0.90
0.75
0.75
TT
—
—
—
—
—
—
—
—
(V)
6–3