DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 742

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–70
Stratix IV Device Handbook Volume 2: Transceivers
Figure 2–37. Sixteen Identical Channels Across Four Transceiver Blocks for Example 8
Common Clock Driver Selection Rules
The common clock driver driving the rx_coreclk ports of all channels must have a
0 PPM frequency difference with respect to the receiver phase compensation FIFO
write clocks of these channels. If there is any frequency difference between the FIFO
read clock (rx_coreclk) and the FIFO write clock, the FIFO overflows or under-runs,
resulting in corrupted data transfer between the FPGA fabric and the receiver.
Channel [15:12]
Channel [11:8]
Channel [3:0]
Channel [7:4]
and Status
and Status
and Status
RX Data
and Status
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
Fabric
FPGA
rx_coreclk[15:12]
rx_coreclk[11:8]
rx_coreclk[3:0]
rx_coreclk[7:4]
Clock Driver
Common
rx_clkout[7:4]
rx_clkout[3:0]
rx_clkout[15:12]
rx_clkout[11:8]
Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Block GXBR3
Transceiver Block GXBR1
Transceiver Block GXBR2
Transceiver Block GXBR0
FPGA Fabric-Transceiver Interface Clocking
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
February 2011 Altera Corporation