DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 610

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–166
Figure 1–132. GIGE Mode for Stratix IV GX Devices
Stratix IV Device Handbook Volume 2: Transceivers
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
PMA-PCS Interface
Interface Frequency
Low-Latency PCS
Fabric-Transceiver
Functional Modes
Fabric-Transceiver
Encoder/Decoder
Channel Bonding
Rate Match FIFO
TX PCS Latency
Interface Frequency
RX PCS Latency
Data Rate (Gbps)
Functional Mode
(Pattern Length)
Interface Width
Byte Ordering
Byte SerDes
Word Aligner
8B/10B
Width
FPGA
FPGA
(MHz)
Figure 1–132
8-bit
Single
Width
10-bit
Basic
shows the GIGE mode configuration supported in Stratix IV GX devices.
16-bit
Double
Width
20-bit
Stratix IV GX Configurations
10-bit
PIPE
XAUI
10-bit
Synchronization
(7-Bit Comma,
State Machine
10-Bit /K28.5/)
Disabled
Automatic
Disabled
Disabled
Enabled
Enabled
GIGE
1.25
GIGE
10-bit
8-Bit
20 - 24
125
Chapter 1: Transceiver Architecture in Stratix IV Devices
x1
5 - 6
Protocol
SRIO
10-bit
SONET
/SDH
8-bit
16-bit
(OIF)
February 2011 Altera Corporation
CEI
Transceiver Block Architecture
10-bit
SDI
10-Bit
Deterministic
Latency
20-Bit