DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 398
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 398 of 1154
- Download datasheet (32Mb)
10–64
Design Security
Stratix IV Device Handbook Volume 1
1
This section provides an overview of the design security feature and its
implementation on Stratix IV devices using the advanced encryption standard (AES).
It also covers the new security modes available in Stratix IV devices.
As Stratix IV devices continue play a role in larger and more critical designs in
competitive commercial and military environments, it is increasingly important to
protect the designs from copying, reverse engineering, and tampering.
Stratix IV devices address these concerns with both volatile and non-volatile security
feature support. Stratix IV devices have the ability to decrypt configuration bitstreams
using the AES algorithm, an industry-standard encryption algorithm that is FIPS-197
certified. Stratix IV devices have a design security feature that utilizes a 256-bit
security key.
Stratix IV devices store configuration data in SRAM configuration cells during device
operation. Because SRAM is volatile, the SRAM cells must be loaded with
configuration data each time the device powers up. It is possible to intercept
configuration data when it is being transmitted from the memory source (flash
memory or a configuration device) to the device. The intercepted configuration data
could then be used to configure another device.
When using the Stratix IV design security feature, the security key is stored in the
Stratix IV device. Depending on the security mode, you can configure the Stratix IV
device using a configuration file that is encrypted with the same key, or for board
testing, configured with a normal configuration file.
The design security feature is available when configuring Stratix IV devices using FPP
configuration mode with an external host (such as a MAX II device or
microprocessor), or when using fast AS or PS configuration schemes. The design
security feature is also available in remote update with fast AS configuration mode.
The design security feature is not available when you are configuring your Stratix IV
device using JTAG-based configuration. For more information, refer to
Configuration Schemes” on page
When using a serial configuration scheme such as PS or fast AS, configuration time is
the same whether or not you enable the design security feature. If the FPP scheme is
used with the design security or decompression feature, a ×4 DCLK is required. This
results in a slower configuration time when compared with the configuration time of
a Stratix IV device that has neither the design security nor the decompression feature
enabled.
Chapter 10: Configuration, Design Security, and Remote System Upgrades in Stratix IV Devices
10–67.
April 2011 Altera Corporation
“Supported
Design Security
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