DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 918

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–72
Table 5–15. EyeQ Interface Register Mapping
Stratix IV Device Handbook Volume 2: Transceivers
0×0
0×1
0×2
0×3
Address
Table 5–15
To control the EyeQ hardware, follow these steps:
1. Read the EyeQ interface register 0×0 (the control and status register) to check the
2. Issue a write to the EyeQ interface register 0×1 (the channel address register) to
3. Issue a write to the EyeQ interface register 0×2 (the eye monitor register address)
4. Issue a write to the EyeQ interface register 0×3 (the data register) to provide the
5. Issue a write to EyeQ interface register 0×0 (the control and status register) to
Control/Status register (EyeQ CSR)
■
■
■
■
■
■
Channel address [15:0]—Specifies the transceiver channel for the desired EyeQ operation. This
must match the logical_channel_address input port.
EyeQ register address [15:0]—Specifies the address EyeQ register to be read from or written to.
The values supported are 0×0 or 0×1.
Data [15:0]—
■
■
busy status. The clear status bit indicates an idle status.
select the desired channel.
to select the desired EyeQ register.
data to be written to the target EyeQ register.
specify read/~write and to issue the start command.
Bit [0]—Start: Writing a 1 to this bit instructs the ALTGX_RECONFIG instance to program the
EyeQ hardware. Writing to this bit automatically clears any error bits.
Bit [1]—Read/Write: Writing a 0 to this bit writes the contents of the data register to one of the
EyeQ registers depending on the address stored in the EyeQ register address register. Writing a
1 reads the contents of the EyeQ register.
Bit [12:2]—11'b00000000000
Bit [13]—Channel address error: This bit is set to 1 if the programmed channel address is
invalid. Writing a 1 to this bit clears the error.
Bit [14]—EyeQ register address error: this bit is set to 1 if the programmed word address is
invalid. Writing a 1 to this bit clears the error.
Bit [15]—Busy status: The value of this bit can be polled to determine if the ALTGX_RECONFIG
read/write request has completed. When this active-high bit is asserted, all registers become
read only until this bit is de-asserted.
For a write operation, the data in this register is written to the EyeQ register selected.
For a read operation, this register contains the contents of the EyeQ register selected. The data
in this register is only valid when the busy status is low. A read operation overwrites the current
contents of this register.
lists the register memory of the 16-bit EyeQ interface registers.
Description
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation