DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 588

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–144
Figure 1–114. Dynamic Switch Signaling in PIPE ×1 Mode
Table 1–54. Transceiver Clock Frequencies Signaling Rates in PCIe ×1 Mode
Stratix IV Device Handbook Volume 2: Transceivers
High-Speed Serial Clock
Low-Speed Parallel Clock
Serial Recovered Clock
Parallel Recovered Clock
FPGA Fabric-Transceiver Interface Clock
FPGA
Fabric
Transceiver Clocks
rateswitch
Interface
PIPE
Figure 1–114
(5 Gbps) data rate.
In PCIe ×1 mode configured at Gen2 (5 Gbps) data rate, when the PCIe rateswitch
controller sees a transition on the rateswitch signal, it sends control signal
pcie_gen2switch to the PCIe clock switch circuitry in the local clock divider block and
the receiver CDR to switch to the instructed signaling rate. A low-to-high transition
on the rateswitch signal initiates a Gen1 (2.5 Gbps) to Gen2 (5 Gbps) signaling
rateswitch. A high-to-low transition on the rateswitch signal initiates a Gen2
(5 Gbps) to Gen1 (2.5 Gbps) signaling rateswitch.
Table 1–54
and 5 Gbps signaling rates.
reset_int
reset_int
Compensation
Compensation
Transceiver
Transmitter
Controller
Receiver
Express
Phase
Phase
Switch
PCS
FIFO
FIFO
Rate
PCI
Dynamic Switch Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signaling Rates in PCIe
x1 Mode
lists the transceiver clock frequencies when switching between 2.5 Gbps
rx_locktorefclk
Output Clock
Output Clock
CMU0_PLL
CMU1_PLL
rx_freqlocked
rx_locktodata
shows the PCIe rateswitch circuitry in PCIe ×1 mode configured at Gen2
signal detect
rx_datain
rx_cruclk
Gen1 (2.5 Gbps) to Gen2 (5 Gbps)
(Low-to-High Transition on the
pcie_gen2switch_done
/1, /2, /4
pcie_gen2switch
/2
250 MHz to 500 MHz
250 MHz to 500 MHz
125 MHz to 250 MHz
1.25 GHz to 2.5 GHz
1.25 GHz to 2.5 GHz
rateswitch Signal)
Transceiver Channel
Frequency
Controller
LTR/LTD
Detector
Detector
Phase
Phase
(PD)
(PD)
Switch
Clock and Data Recovery (CDR) Unit
/1, /2, /4
Local Clock Divider
PCI Express
Clock Switch
pcie_gen2switch
Circuitry
Chapter 1: Transceiver Architecture in Stratix IV Devices
Loop Filter
Pump +
Charge
PCI Express Clock Switch Circuitry
1
0
V
/M
CO
Gen2 (5 Gbps) to Gen1 (2.5 Gbps)
(High-to-Low Transition on the
/2
/4, /5, /8, /10
500 MHz to 250 MHz
500 MHz to 250 MHz
250 MHz to 125 MHz
2.5 GHz to 1.25 GHz
2.5 GHz to 1.25 GHz
/L
rateswitch Signal)
February 2011 Altera Corporation
Transceiver Block Architecture
Switch
Serial Recovered Clock
Parallel Recovered Clock
High-Speed Serial Clock
Low-Speed Parallel Clock