DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 893

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–22. .mif Write Transaction in Channel and CMU PLL Reconfiguration Mode
Notes to
(1) The logical_channel_address port is set to 2’b01 to reconfigure the second transceiver channel.
(2) The rx_tx_duplex_sel[1:0] port is set to 2’b00 to match the Receiver and Transmitter configuration of the specified transceiver channel.
February 2011 Altera Corporation
logical_channel_address[1:0]
reconfig_address_out[5:0]
Figure
channel_reconfig_done
reconfig_mode_sel[2:0]
rx_tx_duplex_sel[1:0]
reconfig_address_en
reconfig_data[15:0]
5–22:
f
reconfig_clk
write_all
Figure 5–22
reconfiguration mode.
For guidelines regarding re-using .mifs, specifying input reference clocks, or using
logical_tx_pll_sel ports, refer to
For more information about reset, refer to the “Reset Sequence when Using Dynamic
Reconfiguration with the Channel and TX PLL select/reconfig Option” section in the
Reset Control and Power Down in Stratix IV Devices
Channel Reconfiguration with Transmitter PLL Select Mode Details
You can reconfigure the data rate of a transceiver channel by switching between a
maximum of four transmitter PLLs.
You can select between the following transmitter PLLs:
■
■
■
busy
CMU PLLs present in a transceiver block
CMU PLLs present in other transceiver blocks
ATX PLLs outside the transceiver block
shows a .mif write transaction when using channel and CMU PLL
1st 16 bits Don’t care
Addr0
2nd 16 bits
Addr1
3’b101
2’b01
2’b00
“Special Guidelines” on page
Stratix IV Device Handbook Volume 2: Transceivers
chapter.
55th 16 bits
Addr54
Don’t care
5–56.
Addr0
5–47