DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 547

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–90. CMU0 Clock Divider
February 2011 Altera Corporation
PCIE_gen2switch_done
CMU0 High-Speed
CMU1 High-Speed
PCIE_gen2switch
Clock Output
Clock Output
f
f
The bandwidth of a PLL is the measure of its ability to track input clock and jitter. It is
determined by the –3 dB frequency of the closed-loop gain of the PLL. There are three
bandwidth settings: high, medium, and low. You can program the PLL bandwidth
setting using the ALTGX MegaWizard Plug-In Manager.
■
■
■
The –3 dB frequencies for these settings can vary because of the non-linear nature and
frequency dependencies of the circuit.
You can power down the CMU0 PLL by asserting the pll_powerdown signal.
For more information, refer to the
chapter.
The high-speed clock output from the CMU0 PLL is forwarded to two clock dividers:
the CMU0 clock divider and the transmitter channel local clock divider. Use the clock
divider only in bonded channel functional modes. In non-bonded functional modes
(such as GIGE functional mode), the local clock divider divides the high-speed clock
to provide clocks for its PCS and PMA blocks. This section only describes the CMU0
clock divider.
For more information about the local clock divider, refer to the “Transceiver Channel
Datapath Clocking” section in the
You can configure the CMU0 clock divider shown in
high-speed clock output from the CMU0 or CMU1 PLLs. The CMU1 PLL is present in the
CMU1 channel.
The high bandwidth setting filters out internal noise from the VCO because it
tracks the input clock above the frequency of the internal VCO noise.
With the low bandwidth setting, if the noise on the input reference clock is greater
than the internal noise of the VCO, the PLL filters out the noise above the –3 dB
frequency of the closed-loop gain of the PLL.
The medium bandwidth setting is a compromise between the high and low
bandwidth settings.
CMU0 Clock Divider
PLL Bandwidth Setting
Power Down CMU0 PLL
/N (1, 2, 4)
CMU0 Clock Divider Block
PCIE rateswitch
circuit
Reset Control and Power Down in Stratix IV Devices
Transceiver Clocking in Stratix IV Devices
0
1
(4, 5, 8, 10)
/S
Stratix IV Device Handbook Volume 2: Transceivers
Figure 1–90
/2
to select the
coreclkout to FPGA Fabric
for Transmitter Channel PCS
High-Speed Serial Clock
Low-Speed Parallel Clock
(for Bonded Modes)
(for Bonded Modes)
(for Bonded Modes)
chapter.
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