DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 314

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

8–36
Stratix IV Device Handbook Volume 1
2.
Figure 8–29. Input Time Delay Assignment Through TimeQuest Timing Analyzer
3.
Figure 8–30. Name Finder Window in Set Input Delay Option
Figure 8–29
clock name must reference the source synchronous clock that feeds the LVDS
receiver. Select the desired clock using the pull-down menu.
Figure 8–30
using the List option in the Name Finder window.
shows the setting parameters for the Set Input Delay option. The
shows the Targets option. You can view a list of all available ports
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
February 2011 Altera Corporation