DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 892

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–46
Stratix IV Device Handbook Volume 2: Transceivers
ALTGX_RECONFIG MegaWizard Plug-In Manager Setup for Channel and CMU PLL
Reconfiguration Mode
To setup channel and CMU PLL reconfiguration mode in the ALTGX_RECONFIG
MegaWizard Plug-In Manager, follow these steps:
1. In the Reconfiguration settings screen, set the What is the number of channels
2. In the Reconfiguration settings screen, select the Channel and TX PLL
The following control signals are always available when you enable the Channel and
TX PLL select/reconfig option:
■
■
The following ports are optional and available for selection in the Channel and TX
PLL Reconfiguration screen:
■
■
■
■
Channel and CMU PLL Reconfiguration Operation
In channel reconfiguration, only a write transaction can occur; no read transactions
are allowed. In the example shown in
two channels. Therefore, the logical_channel_address signal is 2 bits wide. Also, the
transceiver channel is configured in Basic mode with the Receiver and Transmitter
configuration.
You can optionally choose to trigger write_all once by selecting the continuous write
operation in the ALTGX_RECONFIG MegaWizard Plug-In Manager. The Quartus II
software then continuously writes all the words required for reconfiguration.
controlled by the reconfig controller? option. For more information, refer to
“Total Number of Channels Option in the ALTGX_RECONFIG Instance” on
page
select/reconfig option.
channel_reconfig_done
reconfig_address_out[5:0]
reset_reconfig_address
reconfig_address_en
logical_tx_pll_sel and logical_tx_pll_sel_en—For more information about
these two ports, refer to
logical_tx_pll_sel_en Ports” on page
rx_tx_duplex_sel[1:0]
5–10.
“Guidelines for logical_tx_pll_sel and
Figure
5–58.
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
5–22, the ALTGX_RECONFIG controls
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation