MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1002

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x118
Reset
DMA Controller
Table 15-10
15.3.1.6
The destination attributes registers, shown in
operation. Stride mode is enabled by setting DATRn[DSME].
Table 15-11
15-16
W
R
0–31
Offset 0x114
Reset
Bits
Bits
2–6
0x198
0x218
0x298
0
—NLWR
0
1
W
R
1
0x194
0x214
0x294
0
Name
SAD
NLWR
Name
describes the fields of the DATRn.
describes the field of the SARn.
—
—
Destination Attributes Registers (DATR n )
2
Source address. This register contains the low-order bits of the 36-bit source address of the DMA transfer.
The contents are updated after every DMA write operation unless the final stride of a striding operation is less
than the stride size, in which case it remains equal to the address from which the last stride began.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
No last write with response. Not valid for flush transaction type.
0 Last write for transfer is a write with target response.
1 Last write for transfer is a write without target response.
Reserved
Figure 15-11. Destination Attributes Registers (DATR n )
—
Figure 15-10. Source Address Registers (SAR n )
Table 15-11. DATR n Field Descriptions
Table 15-10. SAR n Field Descriptions
6
Figure
DSME
7
All zeros
15-11, contain the transaction attributes for the DMA
All zeros
SAD
Description
8
Description
—
11
DWRITETTYPE
12
15 16
Freescale Semiconductor
Access: Read/Write
—
Access: Read/Write
27 28
EDAD
31
31