MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1512

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Global Utilities
Table 23-14
23-20
10-15
16-17
19-31
Bits
0-9
18
CORE_SPD Requested core clock speed
e500_Ratio
describes PMJCR fields.
Name
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Requested clock ratio between e500 core and CCB clock:
000010 Reserved
000011 3:2
000100 2:1
000101 5:2
000110 3:1
000111 7:2
001000 4:1
001001 Reserved
Default value is the same as PORPLLSR[e500_Ratio].
The value written to this register takes effect when the system wakes from deep sleep or when
a jog mode request is initiated.
Note that if this register has been written by software, but deep sleep has not occurred , then the
value in this register may not necessarily reflect the current clock ratio between the e500 core
and CCB clock.
Reserved
0 Core frequency at or below 800 MHz
1 Core frequency above 800 MHz
Default value is the same as PORDEVSR[CORE_SPD].
The value written to this register takes effect when the system wakes from deep sleep or when
a jog mode request is initiated.
Note that if this register has been written by software, but deep sleep has not occurred , then the
value in this register may not necessarily reflect the current core clock speed. However, this value
must be consistent at all times with the value programmed in PMJCR[e500_Ratio].
Reserved
Table 23-14. PMJCR Field Descriptions
Description
Freescale Semiconductor

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