MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 598

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
I
11.3.1.1
Figure 11-2
when addressed as a slave. Note that this is not the address that is sent on the bus during the address-calling
cycle when the I
Table 11-4
11.3.1.2
Figure 11-3
Determining the I
of I2CFDR and I2CDFSRR.
11-6
2
C Interfaces
Bits
0–6
7
ADDR Slave address. Contains the specific slave address that is used by the I
Name
describes the fields of I2CADR.
shows the I2CADR register, which contains the address to which the I
shows the bits of the I
Offset I
Reset
I
I
Offset I
Reset
2
2
mode of the I
conditions that can cause I2CSR[MIF] to be set, signaling an interrupt pending condition.
Reserved
C Address Register (I2CADR)
C Frequency Divider Register (I2CFDR)
W
R
2
W
R
C module is in master mode.
2
I
C Frequency Divider Ratio for SCL, for additional guidance regarding the proper use
2
2
I
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
C1: 0x000
C2: 0x100
2
2
C1: 0x004
C2: 0x104
0
0
2
Figure 11-3. I
C interface is slave mode for an address match. Note that an address match is one of the
Figure 11-2. I
1
Table 11-4. I2CADR Field Descriptions
2
C frequency divider register. Refer to application note AN2919,
2
C Frequency Divider Register (I2CFDR)
2
2
C Address Register (I2CADR)
ADDR
All zeros
All zeros
Description
FDR
2
C interface. Note that the default
Access: Read/Write
Access: Read/Write
6
2
C interface responds
Freescale Semiconductor
7
7

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