MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 451

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SEC processing of a descriptor sometimes includes writing the original header dword back to system
memory with certain fields modified. The modified fields are shown in the “Writeback” rows of
Figure 10-3
Freescale Semiconductor
12–15
16–23
24–28
4–11
Bits
0–3
29
Writeback
Writeback
Field
Field
DESC_TYPE
and described in
EU_SEL0
EU_SEL1
EU_SEL0
32
MODE0
MODE1
OP_0:
OP_1:
Name
—
0
—
34
DONE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
ICCR0
35
3
OP_0
36
4
MODE0
Primary execution unit select: See
and EU_SEL1,”
Primary mode: Mode data used to program the primary EU. The mode data is specific to the
chosen EU. This field is passed directly to bits 56–63 of the mode register in the selected EU.
Refer to the EU-specific mode register sections
Section 10.7.2.1, “AFEU Mode
Section 10.7.4.1, “DEU Mode
Section 10.7.6.2, “MDEU Mode
Section 10.7.8.1, “RNGU Mode
register beyond bits 56–63 are under control of the channel and not the MODE0 field.
Secondary EU select: See
EU_SEL1,”
Secondary mode: Mode data used to program the primary EU. The mode data is specific to
the chosen EU. This field is passed directly to bits 56–63 of the mode register in the selected
EU. Refer to the EU-specific mode register sections (sections
Register,” and
Descriptor Type: This, along with the DIR field, determines the sequence of actions to be
performed by the channel and selected EUs using the blocks of data listed in the rest of the
descriptor. The attributes determined include the direction of data flow for each data block,
which EU (primary or secondary) is accessed, what snooping options are used, and address
offsets for internal EU accesses.
See
Reserved
37
7
Table
—
Section 10.3.2.2, “Selecting Descriptor Type—DESC_TYPE,”
42
Table 10-4. Header Dword Bit Definitions
8
10-5.
11
43
ICCR1
for possible values.
Figure 10-3. Header Dword
EU_SEL1
Section 10.7.6.2, “MDEU Mode
12
44
for possible values.
15
45
OP_1
16
Section 10.3.2.1, “Selecting Execution Units—EU_SEL0 and
—
Register,”
MODE1
Register,”
Register,”
Register”) for further info. Any bits of any use in any mode
47
—
Section 10.3.2.1, “Selecting Execution Units—EU_SEL0
Description
Section 10.7.5.1, “KEU Mode Register
23
48
Section 10.7.3.2, “CRCU Mode
Section 10.7.7.1, “PKEU Mode Register,”
—
Register”) for further info.
24
(Section 10.7.1.2, “AESU Mode
DESC_TYPE
ID_TAG
Section 10.7.3.2, “CRCU Mode
for possible values.
28
Security Engine (SEC) 3.0
—
29
Register,”
DIR
30
(KEUMR),”
Register,”
and
DN
31
63
10-21