MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 56

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure
Number
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
lvi
L2 Control Register (L2CTL) ............................................................................................... 6-10
Cache External Write Address Registers (L2CEWARn) ...................................................... 6-13
Cache External Write Address Registers Extended Address (L2CEWAREAn)................... 6-14
Cache External Write Control Registers (L2CEWCR0–L2CEWCR3) ................................ 6-14
L2 Memory-Mapped SRAM Base Address Registers (L2SRBARn)................................... 6-16
L2 Memory-Mapped SRAM Base Address Registers Extended Address 0–1
L2 Error Injection Mask High Register (L2ERRINJHI) ...................................................... 6-18
L2 Error Injection Mask Low Register (L2ERRINJLO) ...................................................... 6-18
L2 Error Injection Mask Control Register (L2ERRINJCTL) ............................................... 6-19
L2 Error Capture Data High Register (L2CAPTDATAHI)................................................... 6-20
L2 Error Capture Data Low Register (L2CAPTDATALO) .................................................. 6-20
L2 Error Syndrome Register (L2CAPTECC) ....................................................................... 6-20
L2 Error Detect Register (L2ERRDET) ............................................................................... 6-21
L2 Error Disable Register (L2ERRDIS) ............................................................................... 6-22
L2 Error Interrupt Enable Register (L2ERRINTEN) ........................................................... 6-22
L2 Error Attributes Capture Register (L2ERRATTR) .......................................................... 6-23
L2 Error Address Capture Register (L2ERRADDRL) ......................................................... 6-24
L2 Error Address Capture Register (L2ERRADDRH)......................................................... 6-25
L2 Error Control Register (L2ERRCTL).............................................................................. 6-25
L2 Cache Line Replacement Algorithm ............................................................................... 6-31
e500 Coherency Module Block Diagram................................................................................ 7-1
ECM CCB Address Configuration Register (EEBACR)........................................................ 7-3
ECM CCB Port Configuration Register (EEBPCR)............................................................... 7-4
ECM IP Block Revision Register 1 (EIPBRR1)..................................................................... 7-5
ECM IP Block Revision Register 2 (EIPBRR2)..................................................................... 7-5
ECM Error Detect Register (EEDR)....................................................................................... 7-6
ECM Error Enable Register (EEER) ...................................................................................... 7-7
ECM Error Attributes Capture Register (EEATR) ................................................................. 7-7
ECM Error Low Address Capture Register (EELADR)......................................................... 7-8
ECM Error High Address Capture Register (EEHADR)........................................................ 7-9
DDR Memory Controller Simplified Block Diagram............................................................. 8-2
Chip Select Bounds Registers (CSn_BNDS)........................................................................ 8-13
Chip Select Configuration Register (CSn_CONFIG) ........................................................... 8-13
Chip Select Configuration Register 2 (CSn_CONFIG_2) .................................................... 8-15
DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) ................................................ 8-16
DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) ................................................ 8-17
DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) ................................................ 8-19
DDR SDRAM Timing Configuration 2 Register (TIMING_CFG_2).................................. 8-21
DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG) .............................. 8-23
DDR SDRAM Control Configuration Register 2 (DDR_SDRAM_CFG_2)....................... 8-26
(L2SRBAREAn) .............................................................................................................. 6-17
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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