MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 797

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.3.2.6
When modified weighted round-robin Tx scheduling is enabled (TCTRL[TXSCHED] = 10), this register
determines the weighting applied to each transmit queue for queues 0 to 3. For priority-based scheduling,
TR03WT has no effect. A description of how queue weights affect eTSEC’s round-robin algorithm
appears in
describes the TR03WT register.
Table 14-21
14.5.3.2.7
When modified weighted round-robin Tx scheduling is enabled (TCTRL[TXSCHED] = 10), this register
determines the weighting applied to each enabled transmit queue for queues 4 to 7. For priority-based
scheduling, TR47WT has no effect. A description of how queue weights affect eTSEC’s modified
weighted round-robin algorithm appears in
Queuing (MWRR).” Figure 14-17
Freescale Semiconductor
16–23 WT2 Weighting value for TxBD ring 2 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a minimum
24–31 WT3 Weighting value for TxBD ring 3 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a minimum
Offset eTSEC1:0x2_4144;
Reset
8–15
Bits Name
0–7
Offset eTSEC1:0x2_4140;
Reset
W
R
W
eTSEC3:0x2_6144
R
WT0 Weighting value for TxBD ring 0 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a minimum
WT1 Weighting value for TxBD ring 1 when TCTRL[TXSCHED] = 10. On each round of the Tx scheduler, a minimum
0
eTSEC3:0x2_6140
0
Section 14.6.5.3.2, “Modified Weighted Round-Robin Queuing (MWRR).” Figure 14-16
of WT0
transmission.
of WT1
transmission.
of WT2
transmission.
of WT3
transmission.
describes the fields of the TR03WT register.
TxBD Ring 0–3 Weighting Register (TR03WT)
TxBD Ring 4–7 Weighting Register (TR47WT)
WT4
WT0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
64 bytes of data are scheduled for transmission from TxBD ring 0. Clearing this field prevents
64 bytes of data are scheduled for transmission from TxBD ring 1. Clearing this field prevents
64 bytes of data are scheduled for transmission from TxBD ring 2. Clearing this field prevents
64 bytes of data are scheduled for transmission from TxBD ring 3. Clearing this field prevents
7
7
8
Figure 14-16. TR03WT Register Definition
Figure 14-17. TR47WT Register Definition
Table 14-21. TR03WT Field Descriptions
8
describes the definition for the TR47WT register.
WT5
WT1
Section 14.6.5.3.2, “Modified Weighted Round-Robin
All zeros
All zeros
15 16
Description
15 16
WT6
WT2
Enhanced Three-Speed Ethernet Controllers
23 24
23 24
Access: Read/Write
Access: Read/Write
WT7
WT3
14-49
31
31