MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 534

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.3.9
The CRCU interrupt mask register, controls the setting of bits in the CRCU interrupt status register, as
described in
set, then the corresponding interrupt status register bit is always zero.
Masking an error bit allows for a hardware error condition to go potentially undetected. Therefore, extreme
care should be taken when masking errors, as invalid results may be produced. It is recommended that
errors only be masked during debug operation. This register may be reset by resetting the CRCU.
The interrupt mask register’s bit fields are shown in
Offset 0x3_F038
10-104
W
R
58–60
62–63
Bits
0
56
57
61
Section 10.7.3.8, “CRCU Interrupt Status
CRCU Interrupt Mask Register
Table 10-44. CRCU Interrupt Status Register Bit Definitions (continued)
Name
IFO
ME
AE
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Mode Error. Bit is set if any of these error conditions is detected:
0 No error detected
1 Mode error
Address Error. An illegal read or write address was detected within the CRCU address
space.
0 No error detected
1 Address Error
Reserved
Input FIFO Overflow. The CRCU Input FIFO was pushed while full.
0 No overflow detected
1 Input FIFO has overflowed
Note: When operated through channel-controlled access, the SEC implements flow
Reserved
• any reserved bit of the Mode register is set
• the ALG field of the Mode register contains an illegal value
Figure 10-47. CRCU Interrupt Mask Register
control, and FIFO size is not a limit to data input size. When operated through
host-controlled access, the CRCU cannot accept FIFO inputs larger than 256
bytes without overflowing.
48
ICE PE IE ERE CE KSE DSE ME AE
49
Figure
Register.” If a CRCU interrupt mask register bit is
50 51
10-47, and defined in
Description
52
53
54
55
56
Table
57 58 59 60
Freescale Semiconductor
10-45.
—
Access: Read/Write
IFO
61
62
—
63