MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 76

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure
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20-6
20-7
20-8
20-9
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
20-20
20-21
20-22
20-23
20-24
20-25
20-26
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
21-10
21-11
21-12
21-13
21-14
21-15
21-16
21-17
21-18
21-19
21-20
lxxvi
Transfer Type Register (XFERTYP)..................................................................................... 20-8
Command Response 0–3 Register (CMDRSPn) ................................................................ 20-11
Buffer Data Port Register (DATPORT) .............................................................................. 20-12
Present State Register (PRSSTAT)...................................................................................... 20-13
Protocol Control Register (PROCTL)................................................................................. 20-17
System Control Register (SYSCTL)................................................................................... 20-19
Interrupt Status Register (IRQSTAT).................................................................................. 20-23
Interrupt Status Enable Register (IRQSTATEN) ................................................................ 20-27
Interrupt Signal Enable Register (IRQSIGEN)................................................................... 20-29
Auto CMD12 Error Status Register (AUTOC12ERR) ....................................................... 20-31
Host Capabilities Register (HOSTCAPBLT)...................................................................... 20-33
Watermark Level Register (WML) ..................................................................................... 20-34
Force Event Register (FEVT) ............................................................................................. 20-35
Host Controller Version Register (HOSTVER) .................................................................. 20-36
DMA Control Register (DCR)............................................................................................ 20-37
eSDHC Buffer Scheme ....................................................................................................... 20-38
DMA CCB Interface Block................................................................................................. 20-40
Command CRC Shift Register............................................................................................ 20-42
Two Stages of Clock Divider .............................................................................................. 20-43
Flow Diagram for Card Detection ...................................................................................... 20-46
Flow Chart for Reset of eSDHC and SD I/O Card ............................................................. 20-47
USB Interface Block Diagram .............................................................................................. 21-1
Capability Registers Length (CAPLENGTH)....................................................................... 21-7
Host Controller Interface Version (HCIVERSION) ............................................................. 21-7
Host Controller Structural Parameters (HCSPARAMS)....................................................... 21-8
Host Control Capability Parameters (HCCPARAMS) ......................................................... 21-8
Device Interface Version (DCIVERSION) ........................................................................... 21-9
Device Control Capability Parameters (DCCPARAMS).................................................... 21-10
USB Command Register (USBCMD) ................................................................................ 21-11
USB Status Register (USBSTS).......................................................................................... 21-13
USB Interrupt Enable (USBINTR) ..................................................................................... 21-16
USB Frame Index (FRINDEX)........................................................................................... 21-17
Periodic Frame List Base Address (PERIODICLISTBASE) ............................................. 21-19
Device Address (DEVICEADDR)...................................................................................... 21-19
Current Asynchronous List Address (ASYNCLISTADDR) .............................................. 21-20
Endpoint List Address (ENDPOINTLISTADDR).............................................................. 21-20
Master Interface Data Burst Size (BURSTSIZE) ............................................................... 21-21
Transmit FIFO Tuning Controls (TXFILLTUNING) ......................................................... 21-22
ULPI Register Access (ULPI VIEWPORT) ....................................................................... 21-23
Configure Flag Register (CONFIGFLAG) ......................................................................... 21-24
Port Status and Control (PORTSC)..................................................................................... 21-25
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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Freescale Semiconductor
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