MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1347

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.2.2
This register indicates various states of the USB module and any pending interrupts. This register does not
indicate status resulting from a transaction on the serial bus. Software clears certain bits in this register by
writing a 1 to them (indicated by a w1c in the bit’s W cell in
Freescale Semiconductor
Offset 0x144
Reset
Reset
Bits
1
0
W
W
R
R
AS
31
15
0
Name
RST
RS
USB Status Register (USBSTS)
PS
14
0
Controller reset. Software uses this bit to reset the controller. This bit is cleared by the controller when the
reset process is complete. Software cannot terminate the reset process early by writing a zero to this
register.
Host mode:
Device mode:
Run/Stop.
Host mode:
Device mode:
0 Stop
1 Run
• When software sets this bit, the host controller resets its internal pipelines, timers, counters, state
• When software sets this bit, the USB controller resets its internal pipelines, timers, counters, state
• When this bit is set, the controller proceeds with the execution of the schedule. The controller continues
• Setting this bit will cause the USB controller to enable a pull-up on D+ and initiate an attach event. This
machines etc. to their initial value. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports. Software should not set this bit when
USBSTS[HCH] is a zero. Attempting to reset an actively running host controller will result in undefined
behavior.
machines etc. to their initial value. Any transaction currently in progress on USB is immediately
terminated. Writing a one to this bit in device mode is not recommended.
execution as long as this bit is set. When this bit is set to 0, the host controller completes the current
transaction on the USB and then halts. The USBSTS[HCH] bit indicates when the USB controller has
finished the transaction and has entered the stopped state. Software should not write a one to this field
unless the controller is in the halted state (that is, USBSTS[HCH] is a one).
control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon
transitioning into high-speed mode. Software should use this bit to prevent an attach event before the
controller has been properly initialized. Clearing this bit will cause a detach event.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
RCL
13
0
Table 21-9. USBCMD Register Field Descriptions (continued)
HCH
12
0
Figure 21-9. USB Status Register (USBSTS)
—
11
0
ULPII
10
0
—
0
9
w1c
SLI
All zeros
0
8
—
Description
w1c
SRI
n
7
Figure
URI
w1c
0
6
21-9).
w1c
AAI
0
5
w1c
SEI
0
4
Universal Serial Bus Interfaces
w1c
FRI
0
3
w1c
PCI
0
2
Access: Mixed
w1c
UEI
0
1
w1c
21-13
UI
16
0
0