MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1219

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The eSPI can be configured as a master in single master environment. The master eSPI generates the
transfer clock SPI_CLK using the eSPI baud rate generator (BRG). The eSPI BRG takes as its input the
platform clock divided by two.
SPI_CLK is a gated clock, active only during data transfers. Four combinations of SPI_CLK phase and
polarity can be configured with the clock invert SPMODEx[CIx] and clock phase SPMODEx[CPx]
register bits.
The eSPI master-in slave-out SPI_MISO signal acts as an input for master devices and as an output for
slave devices. Conversely, the master-out slave-in SPI_MOSI signal is an output for master devices and
an input for slave devices. However, it also acts as a second input for master devices and as a second output
for slave devices when using Winbond dual output read.
SPI_CLK is the clock output signal that shifts received data in from SPI_MISO and transmitted data out
to SPI_MOSI. eSPI masters must output a slave select signal to enable eSPI slave devices.
18.3
Table 18-3
a cross-reference to the complete description of each register. Note that the full register address is
comprised of CCSRBAR together with the SPI block base address and offset listed in
Undefined 4-byte address spaces within offset 0x000–0xFFF are reserved.
Freescale Semiconductor
0x018–0x01C Reserved
Memory Map/Register Definition
Offset
0x00C
0x02C
0x000
0x004
0x008
0x010
0x014
0x020
0x024
0x028
shows the memory mapped registers of the eSPI and their offsets. It lists the offset, name, and
Enhanced Serial Peripheral Interface (eSPI)—Block Base Address 0x0_7000
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
SPMODE—eSPI mode register
SPIE—eSPI event register
SPIM—eSPI mask register
SPCOM—eSPI command register
SPITF—eSPI transmit FIFO access register
SPIRF—eSPI receive FIFO access register
SPMODE0—eSPI CS0 mode register
SPMODE1—eSPI CS1 mode register
SPMODE2—eSPI CS2 mode register
SPMODE3—eSPI CS3 mode register
Register
Table 18-3. eSPI Registers
Access
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
0x0000_100F
0x0020_0000
0x0000_0000
0x0000_0000
0x0010_0000
0x0010_0000
0x0010_0000
0x0010_0000
Reset Value
—
—
Enhanced Serial Peripheral Interface
—
18.3.1.5/18-10
18.3.1.6/18-11
18.3.1.7/18-12
18.3.1.7/18-12
18.3.1.7/18-12
18.3.1.7/18-12
Section/Page
18.3.1.1/18-6
18.3.1.2/18-6
18.3.1.3/18-7
18.3.1.4/18-9
Table
18-3.
18-5