MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 144

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Memory Map
address space can be supported.See
detailed description of the PCI Express outbound ATMU windows.
2.2.5
Inbound address translation and mapping refers to the translation of an address from the external address
space of an I/O interface (such as PCI address space) to the local 36-bit address space understood by the
internal interfaces of the MPC8536. It also refers to the mapping of transactions to a particular target
interface and the assignment of transaction attributes. The PCI and the PCI Express controllers have
inbound address translation and mapping units (ATMUs).
2.2.5.1
The PCI controller has three general inbound ATMU windows plus a dedicated window for memory
mapped configuration accesses (PCSRBAR). These windows have a one-to-one correspondence with the
base address registers in the PCI programming model. Updating one automatically updates the other. There
is no default inbound window; if a PCI address does not match one of the inbound ATMU windows, the
device does not respond with an assertion of PCI_DEVSEL. See
Registers,”
2.2.5.2
The PCI Express controller has three inbound ATMU windows plus a default. See
Express Outbound ATMU Registers,”
2.2.5.3
Since both local access windows and inbound ATMUs map transactions to a target interface, it is essential
that they not contradict one another. For instance, it is a programming error to have an inbound ATMU map
a transaction to the DDR SDRAM memory controller (target interface 0b1111) if the resulting translated local
address is mapped to PCI (target interface 0b0000) by a local access window. Such a programming error may
result in unpredictable system deadlocks.
2.3
All of the memory mapped configuration, control, and status registers in the MPC8536 are contained
within a 1-Mbyte address region. To allow for flexibility, the configuration, control, and status block is
relocatable in the local address space. The local address map location of this register block is controlled
by the configuration, control, and status registers base address register (CCSRBAR), see
“Configuration, Control, and Status Registers Base Address Register (CCSRBAR).”
CCSRBAR is 4 Gbytes–9 Mbytes, or 0x0_FF70_0000.
2-10
Configuration, Control, and Status Register Map
for a detailed description of the PCI inbound ATMU windows.
Inbound Address Translation and Mapping Windows
PCI Inbound ATMU
PCI Express Inbound ATMU
Illegal Interaction Between Inbound ATMUs and Local Access Windows
The configuration, control, and status window must not overlap a local
access window that maps to the DDR controller. Otherwise, undefined
behavior occurs.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 17.3.5.1, “PCI Express Outbound ATMU Registers”
for a description of the PCI Express inbound ATMU windows.
NOTE
Section 16.3.1.3, “PCI ATMU Inbound
Section 17.3.5.1, “PCI
The default value for
Freescale Semiconductor
Section 4.3.1.1.2,
for a