MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1250

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
Table 19-16
19.3.4
19.3.4.1
TransCfg, shown in
Table 19-17
19-20
Offset 0x1_8140
Reset 0
Offset 0x1_810C
Reset
W
R
31–16
15–0
W
31
Bit
R
31–16
15–5
4–0
Bit
31
0
Control Status Registers
describes the SNotification fields.
describes the TransCfg fields.
Transport Layer Configuration Register (TransCfg)
0
Notify n
Name
—
0 1
RX_WATER_
DFIS_SIZE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure
Figure 19-16. SATA Interface Notification Register (SNotification)
MARK
Figure 19-17. Transport Layer Configuration Register (TransCfg)
Name
—
0
Reserved, should be cleared.
Represents whether a particular device with the corresponding PM port number n has
sent a set device bits FIS to the host with the notification bit set.
DFIS_SIZE
19-17, controls the configuration of the transport layer.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Table 19-16. SNotification Field Descriptions
Data FIS framing length words. Determines the maximum length each data FIS
should be.
Reserved
This sets the number of locations in the 58-deep Rx FIFO that can be used before
the transport layer instructs the link layer to transmit HOLDS to the transmitting
end. Note that it can take some time for the HOLDs to get to the other end, and
that in the interim there must be enough room in the FIFO to absorb all data that
could arrive. An initial value of 22 is recommended.
Table 19-17. TransCfg Field Descriptions
—
16 15
All zeros
Description
16 15
Description
—
Notify n
Freescale Semiconductor
4
RX_WATER_MARK
Access: Read/Write
3
0
Access: w1c
1
1
0
0
0