MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1599

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 25-15
Freescale Semiconductor
21–23 STRT Start condition. Specifies the event that arms the trace buffer to start looking for the programmed event
24–28
29–31 STOP Trace stop mode. Specifies the event that stops the updating of the trace buffer after it has been started. Trace
Offset 0x044
Reset
11–15
Bits
8–10
Bits
0–4
5–7
W
R
0
Name
Name
IFSEL Interface selection. Specifies the interface that sources information for both comparison/buffer control and
—
SID
—
—
describes the TBCR1 fields.
—
000 No event. Armed immediately
001 Watchpoint monitor event is detected
010 Trace buffer event is detected
011 Performance monitor signals overflow
100 TRIG_IN transitions from 0 to 1
101 TRIG_IN transitions from 1 to 0
110 Current context ID equals programmed context ID
111 Current context ID does not equal programed context ID
Reserved
buffer only stops after it has been triggered at least once.
000 Buffer is full
001 Watchpoint monitor event is detected
010 Trace buffer event is detected
011 Performance monitor signals overflow
100 TRIG_IN transitions from 0 to 1
101 TRIG_IN transitions from 1 to 0
110 Current context ID equals programmed context ID
111 Current context ID does not equal programed context ID
Reserved
buffer data capture.
000 Selects e500 coherency module (ECM) dispatch interface
001 Selects internal DDR SDRAM interface
010 Selects internal PCI outbound interface
011 Reserved
100 Selects internal PCI Express 1 outbound interface
101 Selects internal PCI Express 2 outbound interface
110 Selects internal PCI Express 3 outbound interface
111 Reserved
Reserved
Source ID. Specifies the source ID associated with TBCR0[SIDEN]. The source ID is defined in
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
4
5
IFSEL
Figure 25-9. Trace Buffer Control Register 1 (TBCR1)
Table 25-14. TBCR0 Field Descriptions (continued)
7
8
Table 25-15. TBCR1 Field Descriptions
—
10
11
SID
All zeros
Description
Description
15 16
—
Debug Features and Watchpoint Facility
26 27
Access: Read/Write
Table
TID
25-26.
25-17
31