MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 141

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2.3.4
Figure 2-4
Table 2-7
2.2.3.5
Figure 2-5
Freescale Semiconductor
Offset LAWSR0: 0x0_0C10
Reset
Offset LAWBAR0: 0x0_0C08
Reset
16–23
24–31
W
Bits
8–31
R
W
Bits
0–7
R
LAWSR1: 0x0_0C30
LAWSR2: 0x0_0C50
LAWSR3: 0x0_0C70
LAWSR4: 0x0_0C90
LAWSR5: 0x0_0CB0
EN
LAWBAR1: 0x0_0C28
LAWBAR2: 0x0_0C48
LAWBAR3: 0x0_0C68
LAWBAR4: 0x0_0C88
LAWBAR5: 0x0_0CA8
0
0
describes LAWBARn fields.
BASE_ADDR Identifies the 24 most-significant address bits of the base of local access window n . The
shows the bit fields of the LAWBARn registers.
Figure 2-4. Local Access Window n Base Address Registers (LAWBAR0–LAWBAR7)
shows the fields of the LAWARn registers.
1
IP_CFG
Name
Local Access Window n Base Address Registers
(LAWBAR0–LAWBAR9)
Local Access Window n Attributes Registers (LAWAR0–LAWAR9)
Name
Figure 2-5. Local Access Window n Attributes Registers (LAWAR0–LAWAR7)
—
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
IP block configuration options
Write reserved, read = 0
specified base address should be aligned to the window size, as defined by LAWAR n [SIZE].
6
Table 2-6. LAIPBRR2 Field Descriptions (continued)
LAWSR6: 0x0_0CD0
LAWSR7: 0x0_0CF0
LAWSR8: 0x0_0D10
LAWSR9: 0x0_0D30
LAWSR10: 0x0_0D50
LAWSR11: 0x0_0D70
LAWBAR6: 0x0_0CC8
LAWBAR7: 0x0_0CE8
LAWBAR8: 0x0_0D08
LAWBAR9: 0x0_0D28
LAWBAR10: 0x0_0D48
LAWBAR11: 0x0_0D68
7
7
TRGT_ID
8
Table 2-7. LAWBAR n Field Descriptions
11 12
All zeros
All zeros
Description
Description
BASE_ADDR
—
25 26
Access: Read/Write
Access: Read/Write
SIZE
Memory Map
31
31
2-7