MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 475

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4.5
Besides the registers described in
for descriptors and scatter/gather link table entries (described in Section
following subsections describe these features.
10.4.5.1
The descriptor buffer (DB) provides read-only access to the descriptor currently being processed by the
channel. All descriptors are 8 dwords long. For descriptor format, see
each channel’s DB are shown in
Note that the DB is working storage and the channel may modify the contents of the DB during processing.
In debug scenarios, it may be useful to read the contents of the DB to determine if a well formed descriptor
is being fetched by the channel. Potential causes of malformed descriptors in the DB include:
10.4.5.2
A pointer dword in the descriptor buffer (DB) refers to a Gather Link Table (GLT) or a Scatter Link Table
(SLT) if the J bit in the dword is set. As a channel works on a DB pointer entry, the GLT/SLT is loaded into
channel memory. Reads from the GLT/SLT are enabled for debug purposes.
Figure 10-15
Freescale Semiconductor
•
•
•
The descriptor is built incorrectly
The descriptor is fully or partially overwritten by some other system bus master before the SEC can
fetch the descriptor
The descriptor is not built at the address written to the fetch FIFO
Channel Buffers and Tables
Descriptor Buffer (DB)
Scatter and Gather Link Tables (SLT, GLT)
summarizes the entry format and address ranges for gather and scatter link table entries.
When extended addresses are enabled (by setting the EAE bit in channel
configuration register), then the FFER’s EPTR field must be written before
or concurrently with the FETCH_ADR field. This is necessary because
writing the least significant byte (bits 56–63) is the “trigger” which causes
the FFER contents to be added to the FIFO.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table
Section 10.4.4, “Channel
10-3.
NOTE
Registers,” each channel has memory allocated
Figure
Section 10.3,
10-2. The address ranges of
Security Engine (SEC) 3.0
“Descriptors”). The
10-45