MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 803

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Bits
17
18
19
20
21
22
23
TUCSEN TCP or UDP Checksum verification enable. See
IPCSEN
FILREN
FSQEN
Name
GHTX
VLEX
LFC
Lossless flow control. When set, the eTSEC determines the number of free BDs (through RQPARM n [LEN]
and RBTPTR n ) in each active ring. Should the free BD count in an active ring drop below its setting for
RQPARM n [FBTHR], the eTSEC asserts link layer flow control.
For full-duplex ethernet connections, the eTSEC emits a pause frame as if TCTRL[TFC_PAUSE] was set.
For FIFO packet interface connections, the RFC signal is asserted.
0 Disabled. This is the default
1 Enabled, calculate the free BDs in each active ring and assert link layer flow control if required.
Enable automatic VLAN tag extraction and deletion from Ethernet frames. Note that VLEX must be
cleared if L2OFF is non-zero.
0 Do not delete VLAN tags from received Ethernet frames.
1 If a VLAN tag is seen after the Ethernet source address, and PRSDEP is non-zero, delete the VLAN
Note that if PRSDEP is cleared, VLEX must be cleared as well. (VLAN tag extraction is only supported
Filer enable. When set, the receive frame filer is enabled. This file accepted frames to a particular RxBD
ring according to rules defined in the filer table. In this case, PRSDEP must not be cleared.
0 Do not search the receive queue filer table for received frames. All received frames are sent to RxBD
1 Search the receive queue filer table for received frames, and let the filer determine the index of the
Note that if PRSDEP is cleared, FILREN must be cleared as well.
Enable single-queue mode for the receive frame filer. This bit is ignored unless FILREN is also set.
0 The filer chooses the RxBD ring using the least significant bits of the virtual queue ID as a ring index.
1 The filer always attempts to file received frames to ring 0, regardless of virtual queue ID. This mode is
Group address hash table extend. By default, the group address hash table is 256 entries (as defined by
registers GADDR0–GADDR7); registers IGADDR0–IGADDR7 are then used to define the individual
address hash table. When this bit is set, the hash table is extended to a total of 512 entries
(IGADDR0–IGADDR7 are then the first 256 entries of the extended 512-entry group address hash table).
0 Both the individual and group hash functions are the 8 MSBs of the CRC-32 of the Ethernet destination
1 The group hash function is the 9 MSBs of the CRC-32 of the Ethernet destination address. The
IP Checksum verification enable. See
0 IPv4 header checksums are not verified by the eTSEC—even if layer 3 parsing is enabled.
1 Perform IPv4 header checksum verification if PRSDEP > 01.
0 TCP or UDP checksums are not verified by the eTSEC—even if layer 4 parsing is enabled.
1 Perform TCP or UDP checksum verification if PRSDEP = 11.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
tag and return the VLAN control word in the frame control block returned with this frame.
when the parser is enabled.)
ring 0 by default.
RxBD ring for each frame.
intended for operating the filer as a packet classification engine.
address.
individual address hash function is unavailable.
Table 14-29. RCTRL Field Descriptions (continued)
Section 14.6.4.3, “Receive Path Off-Load.”
Description
Section 14.6.4.3, “Receive Path Off-Load.”
Enhanced Three-Speed Ethernet Controllers
14-55