MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 781

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.3.1.5
Figure 14-6
disable an error interruption, possibly to avoid spurious error indications external to the eTSECs.
Freescale Semiconductor
Offset eTSEC1:0x2_4018;
Reset
Reset
17–19
25–26
Bits
13
14
15
16
20
21
22
23
24
27
28
29
30
31
W
W
R
R
eTSEC3:0x2_6018
16
0
—
MMWREN
MMRDEN
GRSCEN
PERREN
XFUNEN
MAGEN
FGPIEN
CRLEN
RXBEN
DPEEN
RXFEN
FIREN
FIQEN
Name
LCEN
describes the definition for the EDIS register. The error disabled register allows the user to
1
—
—
Error Disabled Register (EDIS)
BSYDIS EBERRDIS
2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Late collision enable
Collision retry limit enable
Transmit FIFO underrun enable
Receive buffer interrupt enable
Reserved
Magic packet received interrupt enable
MII management read completion interrupt enable
MII management write completion interrupt enable
Graceful receive stop complete interrupt enable
Receive frame interrupt enable
Reserved
Filer general purpose interrupt enable
Filer invalid result interrupt enable
Filed frame to invalid queue interrupt enable
Data parity error interrupt enable
Receive frame parse error enable
3
Table 14-9. IMASK Field Descriptions (continued)
Figure 14-6. EDIS Register Definition
4
—
—
6
BABTDIS — TXEDIS
7
All zeros
All zeros
8
Description
9
10
Enhanced Three-Speed Ethernet Controllers
27
—
FIRDIS FIQDIS DPEDIS PERRDIS
12
28
LCDIS CRLDIS XFUNDIS
13
29
Access: Read/Write
14
30
15
31
14-33