MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 488

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.1.1
For CCM, GCM, CMAC (OMAC1), and XCBC-MAC cipher modes, the AESU includes an ICV checking
feature which can generate an ICV and compare it to another supplied ICV.
There are two methods for returning the pass/fail result of ICV checking to the host:
10.7.1.2
The AESU mode register contains 11 non-reserved bits which are used to program the AESU. The mode
register is cleared when the AESU is reset or re-initialized. Setting a reserved AESU mode register bit
generates a data error. If the mode register is modified during processing, a context error is generated.
Figure 10-21
register’s values are set by the descriptor header (see
Dword”).
10-58
50–52
0–49
Bits
Offset 0x3_4000
Reset
•
•
W
R
The ICV check result can be sent to the host by a writeback of EU status fields into host memory.
This is enabled as follows:
— Set either the IWSE or AWSE bit in the channel configuration register (see
— Set the ICE bit in the interrupt mask register
In this case the normal done signaling (by interrupt or writeback) is undisturbed.
The ICV checking result can be sent to the host by interrupt. This is enabled as follows:
— Clear the ICE bit in the interrupt mask register
— Clear both IWSE and AWSE bits in the channel configuration register.
In this case, then the normal done signaling (by interrupt or writeback) occurs if there is no ICV
mismatch. If an ICV mismatch occurs, then an error interrupt is sent to the host, but no channel
done interrupt or writeback.
0
“Channel Configuration Register
Register”).
Name
SCM
ICV Checking in AESU
AESU Mode Register
shows the AESU mode register, and
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Sub-Cipher Mode. Specifies additional options specific to particular cipher modes.
• XOR cipher mode: specifies the number of sources to be XORed together. Valid values are 2-6.
For all other cipher modes, this field must be 0.
Table 10-22. AESU Mode Register Field Descriptions
—
Figure 10-21. AESU Mode Register
(CCR)”)
49 50
Table 10-22
SCM
All zeros
Section 10.3.2, “Descriptor Format: Header
52 53
(Section 10.7.1.8, “AESU Interrupt Mask
Description
—
describes its fields. In normal operation, the
55
56
ECM
57
AUX2 AUX1 AUX0
58
59
Freescale Semiconductor
Section 10.4.4.1,
Access: Read/Write
60
61
CM
62
ED
63