MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1580

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Outbound Static Queue 0 start (Duration
Threshold)
Atomic reservation time-outs for ECM
port
Cycles a read is taking in GPCM
Cycles a read is taking in UPM
Cycles a write is taking in GPCM
Cycles a write is taking in UPM
Core instruction accesses to L2 that hit
Core instruction accesses to L2 that miss
Core data accesses to L2 that hit
Core data accesses to L2 that miss
Non-core burst write to L2 (cache
external write or SRAM)
Non-core non-burst write to L2
Noncore write misses cache external
write window and SRAM memory range
Non-core read hit in L2
Non-core read miss in L2
L2 allocations based on core-initiated
accesses. The data may come from any
source.
L2 retries due to full write queue
L2 retries due to address collision
L2 failed lock attempts due to full set
L2 victimizations of valid lines
L2 invalidations of lines
L2 clearing of locks
External event
Watchpoint monitor hits
Trace buffer hits
Device Performance Monitor
24-26
Event Counted
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 24-10. Performance Monitor Events (continued)
Number
C6:118
C1:117
C2:122
C4:120
C5:114
C2:123
C4:121
C5:115
C6:120
C7:116
C1:118
C2:124
C3:122
C4:122
C5:116
C6:121
C7:117
C3:125
C2:125
C1:122
Ref:59
Ref:23
Ref:24
Ref:25
Ref:22
L2 Cache/SRAM Events
Local Bus Events
DUART Events
Debug Events
Lifetime of OSQ entry 0.
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Number of cycles trig_in pin is asserted
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Description of Event Counted
Freescale Semiconductor