MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1089

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
driven to 0b00 during the address phase for type 0 configuration cycles. The PCI controller implements
address stepping on configuration cycles so that the target’s IDSEL, which is connected directly to one of
the PCI_AD lines, reaches a stable value. This means that a valid address and command are driven on
PCI_AD[31:0] and PCI_C/BE[3:0] one clock cycle before the assertion of PCI_FRAME.
16.4.2.11.5 Type 1 Configuration Translation
For type 1 translations, the PCI controller copies the 30 high-order bits of the PCI CFG_ADDR register
(without modification) onto the PCI_AD[31:2] signals during the address phase. The PCI controller
automatically translates PCI_AD[1:0] into 0b01 during the address phase to indicate a type 1 configuration
cycle.
16.4.2.12
Other Bus Transactions
There are two other PCI transactions that the PCI controller supports—interrupt acknowledge and special
cycles. As an initiator, the PCI controller may initiate both interrupt acknowledge and special-cycle
transactions; however, as a target, the PCI controller ignores interrupt-acknowledge and special-cycle
transactions. Both transactions make use of the PCI CFG_ADDR and PCI CFG_DATA registers described
in
Section 16.4.2.11.3, “Agent Accessing the PCI Configuration Space.”
16.4.2.12.1 Interrupt-Acknowledge Transactions
The PCI bus supports an interrupt-acknowledge transaction. The interrupt-acknowledge command is a
read operation implicitly addressed to the system interrupt controller. Note that the PCI
interrupt-acknowledge command does not address the device’s PIC processor interrupt-acknowledge
register and does not return the interrupt vector address from the PIC unit. See
Chapter 9, “Programmable
Interrupt Controller (PIC),”
for more information about the PIC unit.
When the PCI controller detects a read to the PCI CFG_DATA register, it checks the enable flag and the
device number in the PCI CFG_ADDR register. If the enable bit is set, the bus number corresponds to the
local PCI bus (bus number = 0x00), the device number is all ones (0b1_1111), the function number is all
ones (0b111), and the register number is zero (0b00_0000), then the PCI controller performs an
interrupt-acknowledge transaction. If the bus number indicates a nonlocal PCI bus, the PCI controller
performs a type 1 configuration cycle translation, similar to any other configuration cycle for which the
bus number does not match.
The address phase contains no valid information other than the interrupt-acknowledge command
(PCI_C/BE[3:0] = 0b0000). Although there is no explicit address, PCI_AD[31:0] are driven to a stable
state, and parity is generated. Only one device (the system interrupt controller) on the PCI bus should
respond to the interrupt-acknowledge command by asserting PCI_DEVSEL. All other devices on the bus
should ignore the interrupt-acknowledge command. As stated previously, the device’s PIC unit does not
respond to PCI interrupt-acknowledge commands.
During the data phase, the responding device returns the interrupt vector on PCI_AD[31:0] when
PCI_TRDY is asserted. The size of the interrupt vector returned is indicated by the value driven on the
PCI_C/BE[3:0] signals.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor
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