MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1361

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
11–10
Bits
13
12
9
8
7
Name
SUSP Suspend.
PO
PP
PR
LS
—
Port owner. Unconditionally goes to a 0 when the configured bit in the CONFIGFLAG register makes a 0 to 1
transition. This bit unconditionally goes to 1 whenever the Configured bit is zero. System software uses this
field to release ownership of the port to a selected the module (in the event that the attached device is not a
high-speed device). Software writes a one to this bit when the attached device is not a high-speed device. A
one in this bit means that an internal companion controller owns and controls the port.
Port owner hand-off is not implemented in this design, therefore this bit is always 0.
Port power. Represents the current setting of the switch (0=off, 1=on). When power is not available on a port
(that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc.
When an over-current condition is detected on a powered port, the PP bit in each affected port is transitioned
by the host controller driver from a one to a zero (removing power from the port).
This feature is implemented in the host controller (PPC = 1).
In a device-only implementation port power control is not necessary, thus PPC and PP = 0.
Line status. Reflect the current logical levels of the USB D+ (bit 11) and D– (bit 10) signal lines. The use of line
status by the host controller driver is not necessary (unlike EHCI), because the connection of FS and LS is
managed by hardware.
00 SE0
10 J-state
01 K-state
11 Undefined
Reserved, should be cleared
Port reset.
Host mode:
Device mode:
1 Port is in reset.
0 Port is not in reset.
This field is zero if Port Power(PP) is zero.
Host mode:
0x Disable
10 Enable
11 Suspend
Device mode:
1 Port in suspend state.
0 Port not in suspend state. Default.
• When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision
• This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register.
• The port enabled bit (PE) and suspend (SUSP) bit define the port states as follows:
• When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The
• The module unconditionally sets this bit to zero when software clears the FPR bit. A write of zero to this bit
• This field is zero if Port Power (PP) is zero in host mode.
• In device mode this bit is a read-only status bit.
2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior
is different from EHCI where the host controller driver is required to set this bit to a zero after the reset
duration is timed in the driver.
blocking occurs at the end of the current transaction if a transaction was in progress when this bit was
written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not
change until the port is suspended and that there may be a delay in suspending a port if there is a
transaction currently in progress on the USB.
is ignored by the host controller. If host software sets this bit to a one when the port is not enabled (that is,
port enabled bit is a zero) the results are undefined.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-22. PORTSC Register Field Descriptions (continued)
Description
Universal Serial Bus Interfaces
21-27