MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1495

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.4
Table 23-3
In this table and in the register figures and field descriptions, the following access definitions apply:
Freescale Semiconductor
CKSTP_OUT
POWER_EN
POWER_OK
CLK_OUT
•
•
•
•
•
Signal
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
Memory Map/Register Definition
summarizes the global utilities registers and their addresses.
I/O
O
O
O
I
Checkstop out
Clock out. Reflects clock signal selected by CLKOCR (see
Register
Power enable
Power OK
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Meaning
Meaning
Meaning
Meaning
Timing Assertion—May occur at any time; may be asserted asynchronously to the input clocks.
Timing Assertion/Negation—Depends on the value of CLKOCR[CLK_SEL].
Timing Assertion—May occur only when a wakeup event occurs.
Timing Assertion—May occur when the power is stable while the power_en signal is asserted
State
State
State
State
Table 23-2. Detailed Signal Descriptions (continued)
(CLKOCR)”).
Asserted—Indicates that the e500 core of the MPC8536E is in a checkstop state. The rest of
Negated—Indicates normal operation. After CKSTP_OUT has been asserted, it is negated
Negation—Must remain asserted until the device has been reset with a hard reset.
Asserted—If CLKOCR[ENB] = 1, clock signal selected by CLKOCR[CLK_SEL] is driven.
High impedance—If CLKOCR[ENB] = 0.
Asserted—Indicates to the external power regulator to toggle the power switch to on mode.
Negated—Indicates to the external power regulator to toggle the power switch to off mode.
Negation—No wakeup events occurs at the device. The timing of the signal is asynchronous;
Asserted—Indicate that power level supplied by the external regulator is stable
Negated—Indicate that power supplied by the external regulator is off or not stable
Negation—Negates asynchronous with power down. The timing of the signal is
the MPC8536E logic remains functional unless.
after the next negation (low-to-high transition) of HRESET.
Reset value is 1.
the signal is stable long enough so its possible to synchronize it.
asynchronous, the signal is stable long enough so its possible to synchronize it.
Description
Section 23.4.1.25, “Clock Out Control
Global Utilities
23-3